Roadmap: SFQ Logic Primitives

Prereqs: Curriculum Home
Next: Clocking, Biasing & Power · Curriculum Home

Pathway Overview

Device physics → RSFQ cells → ERSFQ / AQFP family cards. Sibling tracks cover clocking/bias, EDA timing, I/O, and memory in more depth.

graph TD
    O1[Why SE] --> O2[History]
    O2 --> O3[Landscape]
    O3 --> Fields[Field guides]
    Fields --> O4[Logic families]
    O4 --> O5[Cryogenics]
    O5 --> N0[Notation]
    N0 --> F0[Superconductivity]
    F0 --> F1[RCSJ]
    F1 --> F2[Flux Quantization]
    F2 --> F3[Loop / SQUID]
    F3 --> F4[Overdamped vs Underdamped]
    F4 --> B1[Phase to Pulse]
    B1 --> B2[Pulse to Logic State]
    B2 --> C0[RSFQ Overview]
    C0 --> C1[JTL]
    C1 --> C2[Splitter / Confluence]
    C2 --> C3[DFF / Retiming]
    C3 --> B4[Resistive Bias to ERSFQ]
    B4 --> C4[ERSFQ]
    C4 --> C5[AQFP]

Reading order

Orientation

1. Why superconducting electronics?
2. History of superconducting electronics
3. Superconducting electronics landscape
4. (Optional) Field guides
5. Where SFQ sits among logic families
6. Cryogenics for electronics

Device → cells

1. SFQ symbol card
2. How to read SFQ notation
3. Superconductivity Intuition
4. Josephson Junction (RCSJ)
5. Flux Quantization
6. Superconducting Loop / SQUID
7. Overdamped vs Underdamped JJ
8. Phase to Pulse
9. Pulse to Logic State
10. RSFQ Logic Overview
11. JTL Interconnects
12. Splitter and Confluence
13. RSFQ DFF and Retiming
14. Resistive Bias to ERSFQ
15. ERSFQ Logic
16. AQFP Logic

Continue on sibling tracks

• Clocking, Biasing & Power
• EDA Timing & Verification
• Cryogenic Interfaces & I/O
• Cryogenic Memory