SFQ Static Timing Analysis Lab

Abstract delays only — not SPICE. Move data arrival vs the capturing clock pulse; watch setup-like and hold-like slack. Numbers are illustrative teaching cartoons.

t_data (ps) 20

Clock skew (ps) +5

Setup req (ps) 8

Hold req (ps) 3

JTL pads (+ps) 0

Epoch mismatch (balance fail)

…

t_data′

20 ps

t_clk (rel)

5 ps

Setup slack

—

Hold slack

—

Verdict

—

Capturing cell timeline · ★ = clock · blue = data · shaded = legal window cartoon

Setup-like: data must arrive early enough before the clock window closes. Hold-like: data must not be so early it races the previous capture. Fix short paths with pads / DFF epochs — same menu as the chapter.