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Roadmap: Clocking, Biasing & Power

Prereqs: SFQ Logic Primitives · RSFQ DFF and Retiming
Next: EDA Timing & Verification · Curriculum Home

Pathway Overview

How clocks meet data, why bias current explodes at scale, and how ERSFQ plus serial biasing / current recycling attack power and supply limits.

graph TD
    Pip[Gate-Level Pipelining] --> Clk[Concurrent / Counter-Flow Clock]
    Clk --> BiasR[Resistive Bias to ERSFQ]
    BiasR --> ERSFQ[ERSFQ Logic]
    ERSFQ --> DC[DC Bias Delivery]
    DC --> Ser[Serial Biasing / Recycling]

Reading order

  1. Gate-Level Pipelining
  2. Concurrent-Flow and Counter-Flow Clocking
  3. Resistive Bias to ERSFQ
  4. ERSFQ Logic
  5. DC Bias Current Delivery
  6. Serial Biasing and Current Recycling

Later (public TBD / private papers)

Resonant clocking, AC flux-bias transformers, measured power tables, CAD for island assignment --- private explainers after this public path.