Gate-Level Pipelining Lab

Two paths meet at a merge. Each stage is one clocked gate/DFF. Pulses advance one stage per beat. Same stage count → same epoch → merge OK. Different counts → wrong epoch (logic error), even if both pulses “exist.”

Path A stages

Path B stages

Pads on B (DFFs)

Unbalanced

Clock beat

A depth

B depth (+pads)

Pads needed

Merge result

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Fork → stages → merge (dots = pulses advancing each clock)

Beat	A position	B position	A epoch @ merge	B epoch @ merge	Merge
Default is unbalanced (A=3, B=1). Click “Run to merge”, then add pads on B until depths match.

Path balancing: pads needed = |depth A − depth B| on the short path. Throughput can stay high (new wave each beat) while cycle latency equals stage depth — different metrics.