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Roadmap: Cryogenic Interfaces & I/O

Prereqs: Overdamped vs Underdamped JJ · SFQ Logic Primitives
Next: Cryogenic Memory · Curriculum Home

Pathway Overview

Why SFQ pulses cannot drive CMOS directly, then the two classic amplifier families: SQUID stacks and 4JL / Suzuki latching drivers.

graph TD
    Pulse[Phase to Pulse] --> Gap[SFQ Pulse to Volt Levels]
    Gap --> SQUID[SQUID Stack Driver]
    Gap --> JL[4JL / Suzuki Latching]
    SQUID --> Mem[Toward hybrid memory I/O]
    JL --> Mem

Reading order

  1. Phase to Pulse
  2. Overdamped vs Underdamped JJ
  3. From SFQ Pulses to Voltage Levels
  4. SQUID Stack Driver
  5. Four-JL Latching Driver

Later (public TBD / private papers)

PAM-3 / multi-level links, thermal/BER co-optimization, SFQ↔AQFP self-resetting interfaces --- private explainers.