SFQ Pulse → Volt-Level Lab

One fluxon has fixed area Φ₀. CMOS wants taller and wider. Stretching alone washes out height. Real I/O must amplify / latch / stack — leave the single-Φ₀ class.

Mode

raw SFQ

Width

~4 ps

V_avg / swing

~0.5 mV

Area

~Φ₀

CMOS-ready?

Raw fluxon: millivolts × picoseconds — a whisper to CMOS / scopes.

Left: SFQ island · Right: semiconductor / instrument timescale (log-ish cartoon)

Voltage gap ~10² · time gap ~10³ (order-of-magnitude). JTL stays in pulse-land. I/O changes physics class (SQUID stacks, 4JL latching — next concept cards).